 |
| Simple
Gates |
|
|
2-input
AND gate |
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|
2-input
NAND/AND gate |
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|
3-input AND gate
|
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|
3-input NAND/AND
gate |
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|
4-input AND gate |
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|
4-input NAND/AND
gate |
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|
2-input exclusive
NOR gate |
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2-input NOR/OR
gate |
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2-input exclusive
OR gate |
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|
3-input NOR/OR
gate |
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2-input NAND gate |
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4-input NOR/OR
gate |
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|
3-input NAND
gate |
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|
4-input NAND gate |
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2-input NOR gate |
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3-input NOR gate |
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|
4-input NOR gate |
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| Complex
Gates |
|
|
Two
2-input ANDs into 2-input NOR |
|
Two 2-input ORs
into 2-input NAND |
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|
Two
3-input ANDs into 2-input NOR |
|
Two 3-input ORs
into 2-input NAND |
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|
Three
2-input AND into 3-input NOR |
|
Three 2-input
ORs into 3-input NAND |
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|
Three
3-input AND into 3-input NOR |
|
Three 3-input
ORs into 3-input NAND |
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|
Four
2-input AND into 4-input NOR |
|
One-Bit half Adder |
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|
Four
3-input ANDs into 4-input NOR |
|
One-Bit full Adder |
|
|
Two
2-input ANDs into 2-input OR |
|
One-Bit half Subtractor |
|
|
Two
3-input ANDs into 2-input OR |
|
One-Bit full Subtractor |
|
|
Three
2-input AND into 3-input OR |
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Three
3-input AND into 4-input OR |
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Four
2-input AND into 4-input OR |
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|
Four
3-input ANDs into 4-inputOR |
|
|
| Inverting
Drivers |
|
|
1 X Inverter |
|
|
3 X Inverter |
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|
2 X Inverter |
|
|
4 X Inverter |
| Internal
3-Stage Drivers |
|
|
1 X 3-Stage Buffer |
|
|
1 X 3-Stage Inverter |
|
|
2 X 3-Stage Buffer |
|
|
2 X 3-Stage Inverter |
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|
3 X 3-Stage Buffer |
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|
3 X 3-Stage Inverter |
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|
4 X 3-Stage Buffer |
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|
5 X 3-Stage Buffer |
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|
| Buffer
Driver |
|
|
1 X Buffer |
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|
2 X Buffer |
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|
3 X Buffer |
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|
4 X Buffer |
|
|
5 X Buffer |
|
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|
| Multiplexers
& Decoders |
|
|
2:1 Digital multiplexer |
|
|
A OR B not decoder |
|
|
2:2 Digital multiplexer |
|
|
A not AND B decoder |
|
|
4:1 Digital multiplexer |
|
|
|
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|
4:2 Digital multiplexer |
|
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|
4:4 Digital multiplexer |
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|
| Sequential
Logic |
|
|
D-type
F/F without set and reset. Output is Q |
|
|
D-type
F/F with active low reset. Output is Q |
|
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D-type
F/F with active low set. Output is Q |
|
|
D-type
F/F with active low set and reset. Output is Q |
|
|
D-type
buffered F/F with active low set. Output is Q and QBAR |
|
|
D-type
buffered F/F with active low reset. Output is Q and QBAR |
|
|
D-type
buffered F/F with active low set and reset. Output is Q and QBAR |
|
|
D-type
buffered F/F without set and reset. Output is Q and QBAR |
|
|
D-type
latch without set and reset. Output is Q |
|
|
D-type
latch with active low reset. Output is Q |
|
|
D-type
latch with active low set. Output is Q |
|
|
D-type
latch with active low set and reset. Output is Q |
|
|
D-type
buffered latch without set and reset. Output is Q and QBAR |
|
|
D-type
buffered latch with active low reset. Output is Q and QBAR |
|
|
D-type
buffered latch with active low set. Output is Q and QBAR |
|
|
D-type
buffered latch with active low set and reset. Output is Q and QBAR |
| Power
Cells |
|
|
Core
cell resistive tie-up to core VDDD bus |
|
|
Core
cell resistive tie-down to core VSSD bus |
| Pad
Cells |
|
|
Generic
power pad |
|
|
Generic
ground pad |
|
|
Corner
pad with decoupling |
|
|
Corner
pad with no decoupling |
|
|
Input
pad with protection |
|
|
Output
pad |
|
|
Bi-Directional
pad with protection |
| 1 |
